1. Field of the Invention
The invention relates to a semiconductor memory and a driving method of a semiconductor memory. More particularly, the invention relates to a semiconductor memory having a ferroelectric capacitor and a driving method of such a memory.
2. Related Background Art
In recent years, an interest in a memory using a ferroelectric substance as a capacitor dielectric film (hereinafter, such a memory is referred to as a xe2x80x9cferroelectric memoryxe2x80x9d) is increasing more and more. The ferroelectric memory stores information by using a spontaneous polarization of a ferroelectric substance. When a polarizing direction is oriented to one direction by once applying a voltage to the ferroelectric capacitor, the polarization remains (referred to as a xe2x80x9cresidual polarizationxe2x80x9d) even if no electric power is supplied after that, and the stored information is held. The ferroelectric memory having such a feature can be used as a non-volatile memory.
Further, in case of a general volatile memory such as a DRAM or the like, a voltage of 10V or more is necessary for writing data. According to the ferroelectric memory, a polarizing direction of the ferroelectric capacitor is reversed by a voltage of a few volts and data can be written. A data writing time of the general non-volatile memory is on the order of microseconds. A polarization reversing time of the ferroelectric memory is on the order of nanoseconds. As mentioned above, the ferroelectric memory is largely expected as a non-volatile memory of the next generation in which the operation of a low voltage and a high speed can be executed.
At present, a ferroelectric memory having a plurality of memory cells comprising MOS transistors (selective transistors) each of which functions as a switching device and ferroelectric capacitors mainly becomes a target of study and development. A construction and the operation of the memory cells of the ferroelectric memory will now be described with reference to FIG. 5.
In case of writing data into a memory cell MC, a word line WL is asserted and a selective transistor Tr is turned on. 0v is applied to a bit line BL and a positive voltage is applied to a plate line PL. Thus, a polarization of a ferroelectric capacitor C is directed to one direction (↑ direction) shown in FIG. 5 and it is stored as information of, for example, xe2x80x9c1xe2x80x9d into the memory cell MC. On the contrary, when a positive voltage is applied to the bit line BL and 0V is applied to the plate line PL, the polarization of the ferroelectric capacitor C is directed to the direction (↓ direction) opposite to the above one direction and it is stored as information of, for example, xe2x80x9c0xe2x80x9d into the memory cell MC.
In case of reading out the information from the memory cell MC, the bit line BL is precharged to 0V and a positive voltage is applied to the plate line PL. If the ferroelectric capacitor C has already been polarized in the opposite direction (↓ direction) (the information xe2x80x9c0xe2x80x9d has been held), the polarizing direction is reversed. On the other hand, if the ferroelectric capacitor C has already been polarized in one direction (↑ direction) (the information xe2x80x9c1xe2x80x9d has been held), the polarizing direction is not reversed. An electric potential of the bit line BL changes in accordance with the polarizing state of the ferroelectric capacitor C. Therefore, by detecting and amplifying a change amount of the electric potential of the bit line BL by a sense amplifier SA connected to the bit line BL, the information stored in the memory cell MC is read out.
The sense amplifier SA amplifies the electric potential of the bit line BL to either the L (low) level (for example, 0V) or the H (high) level (for example, a power potential Vcc) by using a reference potential Vref as a reference.
Generally, a dummy memory cell (not shown) in which information opposite to that in the memory cell MC is stored is provided for the ferroelectric memory. The reference potential Vref is inputted from the dummy memory cell to the sense amplifier SA. In this case, one information is stored by two memory cells in which complementary data is stored, respectively. Such a memory configuration is called a 2-transistor/2-capacitor (2T/2C) type.
As a memory configuration of the DRAM, a 1-transistor/1-capacitor (1T/1C) type in which one information is stored by one memory cell is used. According to the memory of the 1T/1C type, as compared with the 2T/2C type, since a layout area of a memory cell array is reduced, a large capacity of the memory can be easily realized.
The conventional ferroelectric memory having the memory array of the 1T/1C type has been disclosed in, for example, JP-A-7-93978. FIGS. 18(a) and 21 of this Official Gazette show circuit constructions of the conventional ferroelectric memory, and FIGS. 18(b) and 22 show the data reading operations thereof.
Although the 1T/1C type has a structural advantage as mentioned above, the use of it to the ferroelectric memory is not progressed due to the following reasons.
In case of the memory of the 1T/1C type, a circuit for generating the reference potential Vref is additionally necessary. In the ferroelectric memory, its circuit construction is more complicated than that of the DRAM.
In case of the DRAM, the bit line is set to xc2xd of the power voltage Vcc, the plate line is set to the power voltage Vcc or 0V, and data is written into the memory cell. After that, in order to read out the data, it is sufficient to precharge the bit line to xc2xd Vcc and activate the word line. An electric potential which is induced to the bit line is set to a voltage which is either higher or lower than xc2xd Vcc in accordance with the data stored in the memory cell. That is, in case of the DRAM, if xc2xd Vcc is used as a reference potential Vref, the stored data can be accurately read out.
Also in case of the ferroelectric memory as a target of the present invention, in a manner similar to the DRAM, an electric potential of the bit line during the data reading operation differs in dependence on contents of the data which is read out. Since an absolute value of the bit line potential differs in dependence on a variation of characteristics of the ferroelectric capacitor, it is not easy to decide such a value at the stage of design. Therefore, it is extremely difficult to generate the reference potential Vref adjusted to an intermediate value of two electric potentials which show a binary value and are induced on the bit line during the data reading operation, that is, an average value of the bit line potential in case of reading out the information xe2x80x9c0xe2x80x9d and the bit line potential in case of reading out the information xe2x80x9c1xe2x80x9d. Unless the reference potential Vref is accurately adjusted to the intermediate value of the two electric potentials induced on the bit line, there is also a possibility that the stored information is erroneously read out.
As mentioned above, hitherto, in case of using the memory array construction of the 1T/1C type for the ferroelectric memory, since the reliability of the data which is read out deteriorates, the memory construction of the 2T/2C type which is disadvantageous to realize a large capacity has to be used.
The invention is made in consideration of the above problems and it is an object of the invention to provide a ferroelectric memory from which stored information can be accurately read out and to provide a driving method of such a memory.
To accomplish the above object, according to the first aspect of the invention, there is provided a semiconductor memory comprising: a first sense amplifier which has a first terminal and a second terminal, compares an electric potential of the first terminal with an electric potential of the second terminal, and outputs an amplified voltage to each of the first and second terminals in accordance with a result of the comparison; a second sense amplifier which has a third terminal and a fourth terminal, compares an electric potential of the third terminal with an electric potential of the fourth terminal, and outputs an amplified voltage to each of the third and fourth terminals in accordance with a result of the comparison; a first bit line connected to the first terminal; a second bit line connected to the second terminal; a third bit line connected to the third terminal; a fourth bit line connected to the fourth terminal; a first memory cell which is connected to the first bit line and has a ferroelectric capacitor; a first dummy memory cell which is connected to the second bit line and has a ferroelectric capacitor polarized to a first direction; a second memory cell which is connected to the third bit line and has a ferroelectric capacitor; a second dummy memory cell which is connected to the fourth bit line and has a ferroelectric capacitor polarized to a second direction opposite to the first direction; and first short-circuit means which can short-circuit the second and fourth bit lines. It is preferable that the first and third bit lines belong to a first area and the second and fourth bit lines belong to a second area which does not overlap with the first area.
In the semiconductor memory of the invention, each of the first and second memory cells is used for storing data of one bit in the data which is stored in the semiconductor memory. Unlike the first and second memory cells, the first and second dummy memory cells operate so that the ferroelectric capacitors are certainly polarized to the opposite directions. That is, if the first dummy memory cell stored, for example, information xe2x80x9c0xe2x80x9d, the second dummy memory cell certainly stores information xe2x80x9c1xe2x80x9d. Under this condition, by reading out the stored information from the first dummy memory cell, an electric potential according to the information xe2x80x9c0xe2x80x9d is induced on the second bit line. By reading out the stored information from the second dummy memory cell, an electric potential according to the information xe2x80x9c1xe2x80x9d is induced on the fourth bit line.
When the stored information is read out from the first dummy memory cell to the second bit line and the stored information is read out from the second dummy memory cell to the fourth bit line, if the second and fourth bit lines are short-circuited by the first short-circuit means, the electric potential of both bit lines is set to the intermediate value (average value) of the electric potentials of the bit lines before the short-circuit.
If the first memory cell, second memory cell, first dummy memory cell, and second dummy memory cell are formed in almost the same size, the electric potential of the short-circuited second and fourth bit lines coincides with an intermediate value (average value) of the electric potential of the first bit line (or the third bit line) at the time when the stored information xe2x80x9c1xe2x80x9d is read out from the first memory cell (or the second memory cell) and the electric potential of the first bit line (or the third bit line) at the time when the stored information xe2x80x9c0xe2x80x9d is read out from the first memory cell (or the second memory cell).
After the short-circuited second and fourth bit lines were released, if the electric potential of the second bit line (second terminal) and the electric potential of the first bit line (first terminal) which was changed by reading out the stored information from the first memory cell are amplified by the first sense amplifier, the stored information in the first memory cell is accurately outputted to the outside. Similarly, if the electric potential of the fourth bit line (fourth terminal) and the electric potential of the third bit line (third terminal) which was changed by reading out the stored information from the second memory cell are amplified by the second sense amplifier, the stored information in the second memory cell is accurately outputted to the outside. In this case, the electric potentials at the second and fourth terminals become the reference potential.
According to the invention, the first and third bit lines belong to the first area and the second and fourth bit lines belong to the second area which does not overlap with the first area. According to the above construction, a situation such that another bit line is arranged between the first and third bit lines and another bit line is arranged between the second and fourth bit lines is prevented. Therefore, the first and second short-circuit means for short-circuiting those bit lines can be also easily arranged.
The semiconductor memory can also further have: a third dummy memory cell which is connected to the first bit line and has a ferroelectric capacitor polarized to a third direction; a third memory cell which is connected to the second bit line and has a ferroelectric capacitor; a fourth dummy memory cell which is connected to the third bit line and has a ferroelectric capacitor polarized to a fourth direction opposite to the third direction; a fourth memory cell which is connected to the fourth bit line and has a ferroelectric capacitor; and a second short-circuit means which can short-circuit the first and third bit lines. According to the above construction, the stored information can be read out from the first and second memory cells at high precision and the stored information can be also read out from the third and fourth memory cells at high precision. In this case, the third and fourth dummy memory cells function as a generating source of the reference potential.
According to the second aspect of the invention, there is provided a driving method of a semiconductor memory, comprising: a first step of reading out information stored in a first memory cell and inducing a first electric potential onto a first bit line; a second step of reading out information stored in a first dummy memory cell having a ferroelectric capacitor polarized to a first direction and inducing a second electric potential onto a second bit line; a third step of reading out information stored in a second dummy memory cell having a ferroelectric capacitor polarized to a second direction opposite to the first direction and inducing a fourth electric potential onto a fourth bit line; a fourth step of short-circuiting the second and fourth bit lines by first short-circuit means after the third step; a fifth step of releasing the short-circuited second and fourth bit lines; and a sixth step of activating a first sense amplifier, comparing an electric potential of the first bit line with an electric potential of the second bit line and outputting an amplified voltage to each of the first and second bit lines in accordance with a result of the comparison.
By forming the first memory cell, first dummy memory cell, and second dummy memory cell in an almost same size, an electric potential of the short-circuited second and fourth bit lines coincides with an intermediate value (average value) of the electric potential of the first bit line at the time when stored information xe2x80x9c1xe2x80x9d is read out from the first memory cell and the electric potential of the first bit line at the time when stored information xe2x80x9c0xe2x80x9d is read out from the first memory cell. Therefore, the stored information in the first memory cell is accurately outputted to the outside.
Further, after the sixth step, it is preferable to execute: a seventh step of writing predetermined information into the first dummy memory cell so that the ferroelectric capacitor which the first dummy memory cell has is polarized to the second direction; and an eighth step of writing predetermined information into the second dummy memory cell so that the ferroelectric capacitor which the second dummy memory cell has is polarized to the first direction. By executing those steps, the polarizing direction of the ferroelectric capacitor which the first dummy memory cell has and the polarizing direction of the ferroelectric capacitor which the second dummy memory cell has are reversed from the initial states, so that the occurrence of an imprint phenomenon in the ferroelectric capacitor is prevented.
According to the third aspect of the invention, there is provided a semiconductor memory comprising: a memory cell having ferroelectric capacitors which can be connected to a first bit line through a switching device; a sense amplifier comparing an electric potential of the first bit line with a reference potential in order to read out data in the memory cell; first and second dummy memory cells having ferroelectric capacitors which can be connected to a second bit line and a third bit line through switching devices in order to apply the reference potential to the sense amplifier; and short-circuit means which short-circuits the second and third bit lines at the time of reading the data, wherein the ferroelectric capacitors of both of the dummy memory cells are mutually polarized to the opposite directions as storage information in the dummy memory cells, when the data is read out, the operation to apply the electric potentials from both of the dummy memory cells to each bit line corresponding thereto is executed in a state where both of the second and third bit lines are mutually electrically shut off, and thereafter, an intermediate value of both electric potentials of both of the second and third bit lines which is obtained by the short-circuit of both of the second and third bit lines by the short-circuit means is supplied as a reference potential to the sense amplifier.
Preferably, each time the data is read out, the polarizing directions of the ferroelectric capacitors of both of the dummy memory cells are sequentially reversed to the opposite directions.
According to the fourth aspect of the invention, there is provided a semiconductor memory comprising: a memory cell having ferroelectric capacitor which can be connected to a first bit line through a switching device; a sense amplifier comparing an electric potential of the first bit line with a reference potential in order to read out data in the memory cell; first and second dummy memory cells having ferroelectric capacitors which can be connected to a second bit line and a third bit line through switching devices in order to apply the reference potential to the sense amplifier; and short-circuit means which short-circuits the second and third bit lines at the time of reading the data, wherein the ferroelectric capacitors of both of the dummy memory cells are mutually polarized to the opposite directions as storage information in the dummy memory cells, and each time the data is read out, the polarizing directions of the ferroelectric capacitors of both of the dummy memory cells are sequentially reversed to the opposite directions.
Preferably, an intermediate value of both electric potentials of the bit lines which are applied from the ferroelectric capacitors of both of the dummy memory cells to each of the bit lines corresponding thereto is supplied as a reference potential to the sense amplifier.
For example, the operation to apply the electric potentials from both of the dummy memory cells to each bit line corresponding thereto is executed in a state where both of the second and third bit lines are mutually electrically shut off, and thereafter, an intermediate value of both electric potentials of both of the second and third bit lines which is obtained by the short-circuit of both of the second and third bit lines by the short-circuit means is supplied as a reference potential to the sense amplifier.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.